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PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Features
* Array Format (5:4): 1,280H x 1,024V (1,310,720 active pixels). Total (incl. dark pixels): 1,312H x 1,048V (1,374,976 pixels) * Pixel Size and Type: 5.2m x 5.2m active-pixel photodiode-type * Color Filter Array: RGB Bayer primary color filters * Optical Format: 1/2-inch * Supply Voltage: 3.0V to 3.6V, 3.3V nominal * Frame Rate: 30 fps progressive scan; programmable * Data Rate: 48 MHz at 48 MHz master clock * Responsivity (green pixels): 1.8 V/lux-sec with source illumination at 550nm * SNRmax: 45dB * Dynamic Range: 61dB * Shutter: Electronic rolling shutter (ERS) * Window Size: SXGA; programmable to any smaller format (VGA, QVGA, CIF, QCIF, etc.) * Programmable Controls: Gain, frame rate, frame size * ADC: On-chip, 10 bit * Power Consumption: * Nominal: 325mW at maximum data rate (3.3V) * Standby: 275W * Operating Temperature: 0C to +70C * Package: 48-pin CLCC * Dark Current at 25C: 20 elec/sec * Q. E. (green): 52% * Temporal Noise: 10e * Saturation Voltage: 1.2V * Pixel Capacity: 40Ke * Conversion Gain: 32 uV/e * Monochrome: * Q.E.: 56% * Dynamic Range: 68.2dB * Responsivity: 2.1 V/lux-sec
MT9M001
Micron Part Number: MT9M001C12ST
Description
The Micron(R) Imaging MT9M001 is an SXGA-format with a 1/2-inch CMOS active-pixel digital image sensor. The active imaging pixel array of 1,280H x 1,024V. It incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. It is programmable through a simple two-wire serial interface. The sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode outputs an SXGA-size image at 30 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data.
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(c)2003 Micron Technology, Inc.
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 1: 48-Pin CLCC
SCAN_EN
43 42 41 40 39 38 37 36 35 34 33 32 31 19 20 21 22 23 24 25 26 27 28 29 30
VAA_PIX
SDATA
45
DGND
AGND
AGND
SCLK
VDD
NC
NC
NC
6
5
4
3
2
1
48
47
46
NC
44
STANDBY TRIGGER NC RESET_BAR NC NC OE_BAR NC AGND VAA AGND AGND
7 8 9 10 11 12 13 14 15 16 17 18
NC FRAME_VALID LINE_VALID STROBE DGND VDD DOUT<9> DOUT<8> DOUT<7> DOUT<6> DOUT<5> PIX_CLK
NC
AGND
DGND
DOUT<0>
DOUT<1>
DOUT<2>
DOUT<3>
DOUT<4>
CLK_IN
VAA
Figure 2: Block Diagram
VDD
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NC
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ELW 'DWD
0,
09005aef80a3e031 MT9M001_DS.fm - Rev. A 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 1:
29 13
Pin Descriptions
SYMBOL CLK_IN OE_BAR TYPE Input Input DESCRIPTION Clock In: Master clock into sensor (48 MHz maximum). Output Enable: OE_BAR when HIGH places outputs DOUT<0-9>, FRAME_VALID, LINE_VALID, PIX_CLK, and STROBE into a tri-state configuration. Reset: Activates (LOW) asynchronous reset of sensor. All registers assume factory defaults. Serial Clock: Clock for serial interface. Standby: Activates (HIGH) standby mode, disables analog bias circuitry for power saving mode. Trigger: Activates (HIGH) snapshot sequence. Tie to digital ground. Serial Data: Serial data bus, requires 1.5K resistor to 3.3V for pull-up. Data Out: Pixel data output bits 0-9, DOUT<9> (MSB), DOUT<0> (LSB). Frame Valid: Output is pulsed HIGH during frame of valid pixel data. Line Valid: Output is pulsed HIGH during line of selectable valid pixel data (see Reg0x20 for options). Pixel Clock: Pixel data outputs are valid during falling edge of this clock. Frequency = (master clock). Strobe: Output is pulsed HIGH to indicate sensor reset operation of pixel array has completed. Analog Ground: Provide isolated ground for analog block and pixel array. Digital Ground: Provide isolated ground for digital block. Analog Power: Provide power supply for analog block, 3.3V 0.3V. Analog Pixel Power: Provide power supply for pixel array, 3.3V 0.3V (3.3V). Digital Power: Provide power supply for digital block, 3.3V 0.3V. No Connect: These pins must be left unconnected.
PIN NUMBERS
10 46 7 8 43 45 24-28, 32-36 41 40 31 39 15, 17, 18, 21, 47, 48 5, 23, 38 16, 20 1 4, 22, 37 2, 3, 6, 9, 11, 12, 14, 19, 30, 42, 44
RESET_BAR SCLK STANDBY TRIGGER SCAN_EN SDATA DOUT<0-9> FRAME_VALID LINE_VALID PIX_CLK STROBE AGND DGND VAA VAA_PIX VDD NC
Input Input Input Input Input Input/Output Output Output Output Output Output Supply Supply Supply Supply Supply -
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PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Pixel Data Format Pixel Array Structure
The MT9M001 pixel array is configured as 1,312 columns by 1,048 rows (shown in Figure 3). The first 16 columns and the first eight rows of pixels are optically black, and can be used to monitor the black level. The last seven columns and the last seven rows of pixels are also optically black. The black row data is used internally for the automatic black level adjustment. However, the black rows can also be read out by setting the sensor to raw data output mode (Reg0x20, bit 11 = 1). There are 1,289 columns by 1,033 rows of optically active pixels, which provides a four-pixel boundary around the SXGA (1,280 x 1,024) image to avoid boundary effects during color interpolation and correction. blue and green color pixels. Likewise, the even numbered columns contain green and blue color pixels, and odd numbered columns contain red and green color pixels.
Figure 4: Pixel Color Pattern Detail (Top Right Corner)
column readout direction . . . black pixels Pixel (8, 16) G row readout direction B ... G B G B R G R G R G G B G B G B R G R G R G G B G B G B R G R G R G G B G B G B
Figure 3: Pixel Array Description
8 black rows (0, 0)
7 black columns
SXGA (1,280 x 1,024) + 4 pixel boundary for color correction + additional active column + additional active row = 1,289 x 1,033 active pixels
16 black columns
Output Data Format
The MT9M001 image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking, as shown in Figure 5. The amount of horizontal blanking and vertical blanking is programmable through Reg0x05 and Reg0x06, respectively. LINE_VALID is HIGH during the shaded region of the figure. FRAME_VALID timing is described in the next section.
(1311, 1047)
7 black rows
The MT9M001 uses a Bayer color pattern, as shown in Figure 4. The even-numbered rows contain green and red color pixels, and odd numbered rows contain
09005aef80a3e031 MT9M001_DS.fm - Rev. A 11/03 EN
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PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 5: Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00
VALID IMAGE
HORIZONTAL BLANKING
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00 Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 VERTICAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL/HORIZONTAL BLANKING 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00
Output Data Timing
The data output of the MT9M001 is synchronized with the PIX_CLK output. When LINE_VALID is HIGH, one 10-bit pixel datum is output every PIX_CLK period.
Figure 6: Timing Example of Pixel Data
....
LINE_VALID
....
PIX_CLK
Blanking Valid Image Data
....
Blanking
DOUT9-DOUT0
P0 (9:0)
P1 (9:0)
P2 (9:0)
P3 (9:0)
P4 (9:0)
....
Pn-1 (9:0)
Pn (9:0)
The rising edges of the PIX_CLK signal are nominally timed to occur on the rising DOUT edges. This allows PIX_CLK to be used as a clock to latch the data. DOUT data is valid on the falling edge of PIX_CLK. The
PIX_CLK is HIGH while master clock is HIGH and then LOW while master clock is LOW. It is continuously enabled, even during the blanking period.
Figure 7: Row Timing and FRAME_VALID/LINE_VALID Signals
...
FRAME_VALID
...
LINE_VALID
...
Number of master clocks
P1
A
Q
A
Q
A
P2
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PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Frame Timing Formulas Table 2: Frame Timing
PARAMETER A P1 P2 Q = P1 + P2 A+Q V Nrows x (A + Q) F NAME Active Data Time Frame Start Blanking Frame End Blanking Horizontal Blanking Row Time Vertical Blanking Frame Valid Time Total Frame Time EQUATION (MASTER CLOCK) (Reg0x04 + 1) (242) (2 + Reg0x05 - 19) (MIN Reg0x05 value = 19) (244 + Reg0x05 - 19) (MIN Reg0x05 value = 19) ((Reg0x04 + 1) + (244 + Reg0x05 - 19)) (Reg0x06 + 1) x (A + Q) (MIN Reg0x06 value = 15) (Reg0x03 + 1) x (A + Q) (Reg0x03 + 1 + Reg0x06 + 1) x (A + Q) DEFAULT TIMING 1,280 pixel clocks = 26.7s 242 pixel clocks = 5.04s 2 pixel clocks = 0.042s 244 pixel clocks = 5.08s 1,524 pixel clocks = 31.75s 39,624 pixel clocks = 825.5s 1,560,576 pixel clocks = 32.51ms 1,600,200 pixel clocks = 33.34ms NOTES 1
2 2
NOTE: 1. Row skip mode should have no effect on the integration time. Column skip mode changes the effective value of Column Size (Reg0x04) as follows: Column Skip 2 => R4eff = (int(R4 / 4) x 2) + 1 Column Skip 4 => R4eff = (int(R4 / 8) x 2) + 1 Column Skip 8 => R4eff = (int(R4 / 16) x 2) + 1 where the int() function truncates to the next lowest integer. Now use R4eff in the equation for row time instead of R4 2. Default for Reg0x05 = 9. However, sensor ignores any value for Reg0x05 less than 19.
Sensor timing is shown above in terms of pixel clock and master clock cycles (please refer to Figure 6). The recommended master clock frequency is 48 MHz. The vertical blank and total frame time equations assume that the number of integration rows (bits 13 through 0 of Reg0x09) is less than the number of active plus
blanking rows (Reg0x03 + 1 + Reg0x06 + 1). If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 3.
Table 3:
PARAMETER V' F'
Frame Time - Long Integration Time
NAME EQUATION (MASTER CLOCK) DEFAULT TIMING 39,624 pixel clocks = 82.5s 1,600,200 pixel clocks = 33.34ms Vertical Blanking (long integration time) (Reg0x09 - Reg0x03) x (A + Q) Total Frame Time (long integration time) (Reg0x09 + 1) x (A + Q)
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PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Serial Bus Description
Registers are written to and read from the MT9M001 through the two-wire serial interface bus. The sensor is a two-wire serial interface slave and is controlled by the two-wire serial interface clock (SCLK), which is driven by the two-wire serial interface master. Data is transferred into and out through the MT9M001 twowire serial interface data (SDATA) line. The SDATA line is pulled up to 3.3V off-chip by a 1.5K resistor. Either the slave or master device can pull the SDATA line down--the two-wire serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. edge bit after each eight-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit.
Bus Idle State
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits.
Start Bit
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH.
Protocol
The two-wire serial interface bus defines several different transmission codes, as follows: * a start bit * the slave device eight-bit address * a(an) (no) acknowledge bit * an eight-bit message * a stop bit
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH.
Slave Address
The eight-bit address of a two-wire serial interface device consists of seven bits of address and 1 bit of direction. A "0" in the LSB (least significant bit) of the address indicates write mode, and a "1" indicates read mode.
Sequence
A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's eight-bit address. The last bit of the address determines if the request will be a read or a write, where a "0" indicates a write and a "1" indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the eight-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. The MT9M001 uses 16-bit data for its internal registers, thus requiring two eight-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and eight-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data eight bits at a time. The master sends an acknowl-
Data Bit Transfer
One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock--it can only change when the serial clock is LOW. Data is transferred eight bits at a time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.
09005aef80a3e031 MT9M001_DS.fm - Rev. A 11/03 EN
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PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Two-Wire Serial Interface Sample Write and Read Sequences 16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 8. A start bit given by the master, followed by the write address, starts the sequence. The image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each eight-bit transfer, the image sensor will give an acknowledge bit. All 16 bits must be written before the register will be updated. After 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit.
Figure 8: Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284
SCLK
SDATA 0xBA ADDR START ACK Reg0x09 ACK 0000 0010 ACK 1000 0100 ACK
STOP
16-Bit Read Sequence
A typical read sequence is shown in Figure 9. First the master has to write the register address, as in a write sequence. Then a start bit and the read address specifies that a read is about to happen from the register. The master then clocks out the register data eight
bits at a time. The master sends an acknowledge bit after each eight-bit transfer. The register address should be incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit.
Figure 9: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK
SDATA 0xBA ADDR START ACK Reg0x09 ACK 0xBB ADDR ACK 0000 0010 ACK 1000 0100 NACK
STOP
09005aef80a3e031 MT9M001_DS.fm - Rev. A 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Registers Register Map Table 4:
Note 1 REGISTER # (HEX) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x09 0x0B 0x0C 0x0D 0x1E 0x20 0x2B 0x2C 0x2D 0x2E 0x35 0x5F 0x60 0x61 0x62 0x63 0x64 0xF1 DESCRIPTION Chip Version Row Start Column Start Row Size (Window Height) Col Size (Window Width) Horizontal Blanking Vertical Blanking Output Control Shutter Width Restart Shutter Delay Reset Read Options 1 Read Options 2 Green1 Gain Blue Gain Red Gain Green2 Gain Global Gain Cal Threshold Cal Green1 Cal Green2 Cal Ctrl Cal Red Cal Blue Chip Enable DATA FORMAT (BINARY) 1000 0100 0001 0001 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0000 0d00 00dd 00dd dddd dddd dddd 0000 0000 0000 000d 0000 0ddd dddd dddd 0000 0000 0000 000d 1000 dddd 00dd dd00 dd01 0dd1 d00d d10d 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd dddd dddd d0dd dddd 0000 000d dddd dddd 0000 000d dddd dddd d00d d100 1001 1ddd 0000 000d dddd dddd 0000 000d dddd dddd 0000 0000 0000 00dd DEFAULT VALUE (HEX) 0x8421 0x000C 0x0014 0x03FF 0x04FF 0x0009 0x0019 0x0002 0x0419 0x0000 0x0000 0x0000 0x8000 0x1104 0x0008 0x0008 0x0008 0x0008 0x0008 0x0904 0x0000 0x0000 0x0498 0x0000 0x0000 0x0001 NOTES 2
Register List and Default Values
3 3 3 3
NOTE: 1. 1 = always 1 0 = always 0 d = programmable 2. Previous version used the data format of 1000 0100 0001 0001; hex value of 0x8411. 3. In default mode, calibration values start at "0" but are set via dark level calibration.
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PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 5:
REGISTER
Register Description
BIT DESCRIPTION
Chip ID 0x00 0-15 This register is read-only and gives the chip identification number: 0x8421. Window Control These registers control the size of the window. 0x01 0-10 First row to be read out--default = 0x000C (12). 0x02 0x03 0x04 0-10 0-10 0-10 First column to be read out--default = 0x0014 (20). Register value must be an even number. Window height (number of rows - 1)--default = 0x03FF (1023). Minimum value for 0x03 = 0x0002. Window width (number of columns - 1)--default = 0x04FF (1279). Register value must be an odd number. Minumum value for 0x04 = 0x0003.
Blanking Control These registers control the blanking time in a row (called column fill-in or horizontal blanking) and between frames (vertical blanking). Horizontal blanking is specified in terms of pixel clocks. Vertical blanking is specified in terms of row readout times. The actual imager timing can be calculated using Table 2, Frame Timing, on page 6. 0x05 0-10 Horizontal Blanking--default = 0x0009 (9 pixels). 0x06 0-10 Vertical Blanking--default = 0x0019 (25 rows). Output Control This register controls various features of the output format for the sensor. 0x07 0 Synchronize changes (copied to Reg0xF1, bit1). 0 = normal operation. Update changes to registers that affect image brightness (integration time, integration delay, gain, horizontal blanking and vertical blanking, window size, row/column skip or row mirror) at the next frame boundary. The "frame boundary" is 8 row_times before the rising edge of FRAME_VALID. (If "Show Dark Rows" is set, it will be coincident with the rising edge of FRAME_VALID.) 1 = do not update any changes to these settings until this bit is returned to "0." 1 Chip Enable (copied to Reg0xF1, bit0). 1 = normal operation. 0 = stop sensor readout. When this is returned to "1," sensor readout restarts at the starting row in a new frame. The digital power consumption can then also be reduced to less than 5uA by turning off the master clock. 2 Reserved--default is 0; set to zero at all times. 3 6 Reserved--default is 0; set to zero at all times. Override pixel data. 0 = normal operation. 1 = output programmed test data (see Reg0x32). First valid columns will output contents of test data register; second columns will output inverted data. Third columns will output noninverted data, fourth inverted, etc.
09005aef80a3e031 MT9M001_DS.fm - Rev. A 11/03 EN
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PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 5:
REGISTER
Register Description (continued)
BIT DESCRIPTION
Pixel Integration Control These registers (along with the window sizing and blanking registers) control the integration time for the pixels. The actual total integration time (tINT) is: t INT = Reg0x09 x row time - overhead time - reset delay, where: Row time = ((Reg0x04 + 1) + 244 + Reg0x05 - 19) pixel clock periods Overhead time = 180 pixel clock periods Reset delay = 4 x Reg0x0C pixel clock periods If the value in Reg0x0C exceeds (row time - 548)/4 pixel clock cycles, the row time will be extended by (4 x Reg0x0C - (row time - 548)) pixel clock cycles. In this expression, the row time term, Reg0x09 x ((number of columns) + 244 + horizontal blanking register - 19), corresponds to the number of rows integrated. The overhead time (180 pixel clocks) is the overhead time between the READ cycle and the RESET cycle, and the final term is the effect of the reset delay. Typically, the value of Reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows) such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, the MT9M001 will add additional blanking rows as needed. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60Hz flicker, this means tINT must be a multiple of 1/120 of a second. Under 50Hz flicker, tINT must be a multiple of 1/100 of a second. 0x09 0-13 Number of rows of integration--default = 0x0419 (1049). 0x0C 0-10 Shutter delay--default = 0x0000 (0). This is the number of master clocks times four that the timing and control logic waits before asserting the reset for a given row. Setting bit 0 to "1" of Reg0x0B will cause the sensor to abandon the readout of the current frame and restart from the first row. This register automatically resets itself to 0x0000 after the frame restart. The first frame after this event is considered to be a "bad frame" (see description for Reg0x20, bit0). This register is used to reset the sensor to its default, power-up state. To put the MT9M001 in reset mode first write a "1" into bit 0 of this register, then write a "0" into bit 0 to resume operation.
Frame Restart 0x0B 0
Reset 0x0D
0
Read Mode 1 In read mode 1, this register is used to control many aspects of the readout of the sensor.
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PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 5:
REGISTER 0x1E
Register Description (continued)
BIT 0 1 2 3 4 5 6 7 8 DESCRIPTION Reserved--default is 0; set to zero at all times. Reserved--default is 0; set to zero at all times. Column Skip 4--default is 0 (disable). 1 = enable. Row Skip 4--default is 0 (disable). 1 = enable. Column Skip 8--default is 0 (disable). 1 = enable. Row Skip 8--default is 0 (disable). 1 = enable. Reserved--default is 0; do not change. Reserved--default is 0; do not change. Snapshot Mode--default is 0 (continuous mode). 1 = enable (wait for TRIGGER; TRIGGER can come from outside signal (TRIGGER pin on the sensor) or from serial interface register restart, i.e. programming a "1" to bit 0 of Reg0x0B. STROBE Enable--default is 0 (no STROBE signal). 1 = enable STROBE (signal output from the sensor during the time all rows are integrating. See STROBE width for more information). STROBE Width--default is 0 (STROBE signal width at minimum length, 1 row of integration time, prior to line valid going HIGH). 1 = extend STROBE width (STROBE signal width extends to entire time all rows are integrating). Strobe Override--default is 0 (STROBE signal created by digital logic). 1 = override STROBE signal (STROBE signal is set HIGH when this bit is set, LOW when this bit is set LOW. It is assumed that STROBE enable is set to "0" if STROBE override is being used). Reserved--default is 0; do not change. Reserved--default is 0; do not change. Reserved--default is 0; do not change. Reserved--default is 1; do not change.
9
10
0x1E
11
12 13 14 15
Read Mode 2 This register is used to control many aspects of the readout of the sensor.
09005aef80a3e031 MT9M001_DS.fm - Rev. A 11/03 EN
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PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 5:
REGISTER 0x20
Register Description (continued)
BIT 0 DESCRIPTION No bad frames--1 = output all frames (including bad frames). 0 (default) = only output good frames. A bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, row or column skip, or mirroring. Reserved--default is 0; do not change. Reserved--default is 1; set to "1" at all times. Column skip--1= read out two columns, and then skip two columns (for example, col 0, col 1, col 4, col 5...). 0 = normal readout (default). Row skip--1 = read out two rows, and then skip two rows (for example, row 0, row 1, row 4, row 5...). 0 = normal readout (default). Reserved--default is 0; do not change. Reserved--default is 0; set to zero at all times. Flip Row--1 = readout starting 1 row later (alternate color pair). 0 (default) = normal readout. Reserved--default is 1; set to "1" at all times. 1 = "Continuous" LINE_VALID (continue producing LINE_VALID during vertical blanking). 0 = normal LINE_VALID (default, no LINE_VALID during vertical blanking). 1 = LINE_VALID = "Continuous" LINE_VALID XOR FRAME_VALID. 0 = LINE_VALID determined by bit 9. Reserved--default is 0; do not change. Reserved--default is 1; do not change. Reserved--default is 0; do not change. Reserved--default is 0; do not change. Mirror Row--1 = read out from bottom to top (upside down). 0 (default) = normal readout (top to bottom).
1 2 3
4
5 6 7 8 9 10 11 12 13 14 15
Gain Settings The gain is individually controllable for each color in the Bayer pattern as shown in the register chart. Formula for gain setting: Gain 8 Gain = (bit[6] + 1) x (bit[5-0] x 0.125) Gain > 8 (bit[6] = 1 and bit[5] = 1) Gain = 8.0 + bit[2-0] Since bit[6] of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. Some settings offer superior noise performance to others, despite the same overall gain. The following lists the recommended gain settings: Gain 1.000 to 4.000 4.25 to 8.00 9.0 to 15.0 0x2B 6-0 0x2C 0x2D 0x2E 6-0 6-0 6-0 Increments 0.125 0.25 1.0 Recommended Settings 0x08 to 0x20 0x51 to 0x60 0x61 to 0x67
Green1 gain--default = 0x08 (8) = 1x gain. Blue gain--default = 0x08 (8) = 1x gain. Red gain--default = 0x08 (8) = 1x gain. Green2 gain--default = 0x08 (8) = 1x gain.
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1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 5:
REGISTER 0x35
Register Description (continued)
BIT 6-0 DESCRIPTION
Global gain--default = 0x08 (8) = 1x gain. This register can be used to set all four gains at once. When read, it will return the value stored in Reg0x2B. Black level Calibration These registers are used in the black level calibration. Their functionality is described in detail in the next section. 0x5F 5-0 Thres_lo--Lower threshold for black level in ADC LSBs--default = 000100. 7 1 = override automatic Thres_hi and Thres_lo adjust (Thres_hi always = bits 14-8; Thres_lo always = bits 5-0). Default = 0 = Automatic Thres_hi and Thres_lo adjustment. Thres_hi--Maximum allowed black level in ADC LSBs (default = Thres_lo + 5). Black level maximum is set to this value when bit 7 = 1; black level maximum is reset to this value after every black level average restart if bit 15 = 1 and bit 7 = 0. No gain dependence. 1 = Thres_lo is set by the programmed value of bits 5-0, Thres_hi is reset to the programmed value (bits 14-8) after every black level average restart. 0 = Thres_lo and Thres_hi are set automatically, as described above. Cal Green1--analog offset correction value for Green 1, bits 0-7 sets magnitude, bit 8 set sign. 2's complement, if bit 8 = 1, Offset = bits [0-7] - 256. 0 = positive. 1 = negative. Cal Green2--analog offset correction value for Green 2, bits 0-7 sets magnitude, bit 8 set sign. 0 = positive. 1 = negative. Manual override of black level correction. 1 = override automatic black level correction with programmed values. 0 = normal operation (default). Force/disable black level calibration. 00 = apply black level calibration during ADC operation only (default). 10 = apply black level calibration continuously. X1= disable black level correction (Offset Correction Voltage = 0.0V). (In this case, no black level correction is possible). Reserved--default is 1; do not change. Reserved--default is 0; do not change. Reserved--default is 1; do not change. Reserved--default is 0; do not change. Reserved--default is 1; do not change. 1 = do not reset the upper threshold after a black level recalculation sweep. 0 = reset the upper threshold after a black level recalculation sweep (default). 1 = start a new running digitally filtered average for the black level (this is internally reset to "0" immediately), and do a rapid sweep to find the new starting point. 0 = normal operation (default). Reserved--default is 0; set to zero at all times. 1 = do not perform the rapid black level sweep on new gain settings. 0 = normal operation. Cal Red--analog offset correction value for Red, bits 0-7 sets magnitude, bit 8 set sign. 2's complement, if bit 8 = 1, Offset = bits [0-7] - 256. 0 = positive. 1 = negative.
14-8
15
0x60
8-0
0x61
8-0
0x62
0
0x62
2-1
4-3 6-5 7 9-8 10 11 12
14-3 15 0x63 8-0
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Table 5:
REGISTER 0x64
Register Description (continued)
BIT 8-0 DESCRIPTION
Cal Blue--analog offset correction value for Blue, bits 0-7 sets magnitude, bit 8 set sign. 2's complement, if bit 8 = 1, Offset = bits [0-7] - 256. 0 = positive. 1 = negative. Chip Enable and Two-wire serial interface write synchronize. 0xF1 0 Mirrors the functionality of Reg0x07 bit1 (Chip Enable). 1 = normal operation. 0 = stop sensor readout; when this is returned to "1," sensor readout restarts at the starting row in a new frame. 1 Mirrors the functionality of Reg0x07 bit0 (Synchronize changes). 0 = normal operation, update changes to registers that affect image brightness (integration time, integration delay, gain, horizontal blanking and vertical blanking, window size, row/column skip, or row/column mirror) at the next frame boundary. 1 = do not update any changes to these settings until this bit is returned to "0."
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Feature Description Signal Path
The MT9M001 signal path consists of two stages, a programmable gain stage and a programmable analog offset stage. Programmable Gain Stage The gain settings can be independently adjusted for the colors Green1, Blue, Red, and Green2 and are programmed through registers 0x2B, 0x2C, 0x2D, and 0x2E, respectively. A total programmable gain of 15 is available and can be calculated using the following formula: Gain 1 to 8: Gain = (bit[6] + 1) x (bit[5-0] x 0.125) For gain higher than eight, the user would need to set bit[6-5] = 11 and use the lower 3 LSB's bit[2-0] to set the higher gain values. The formula for obtaining gain greater than eight is as follows: Total gain = 8 + bit[2-0] For example, for total gain = 12, the value to program is bit[6-0] = 1100100. The maximum total gain = 15, i.e. bit[6-0] = 1100111. The gain circuitry in the MT9M001 is designed to offer signal gains from one to 15. The minimum gain of one corresponds to the lowest setting where the pixel signal is guaranteed to saturate the ADC under all specified operating conditions. Any reduction of the gain below this value may cause the sensor to saturate at ADC output values less than the maximum, under certain conditions. It is recommended that this guideline be followed at all times. Since bit[6] of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. Some settings offer superior noise performance to others, despite the same overall gain. Recommended gain settings are listed in Table 6.
Figure 10: Signal Path
Gain Selection (Reg0x2B - 0x2E)
Pixel Output (signal minus reset)
X
+
10-bit ADC
ADC Data (9:0)
Offset Correction Voltage (Reg0x60, Reg0x61, Reg0x63, Reg0x64) (signed lower 9bits) x 2mV
Table 6:
Recommended Gain Settings at 48 MHz
INCREMENTS 0.125 0.25 1.0 RECOMMENDED SETTINGS 0x08 to 0x20 0x51 to 0x60 0x61 to 0x67
NOMINAL GAIN 1 to 4.000 4.25 to 8.00 9 to 15
Programmable Analog Offset Stage The programmable analog offset stage corrects for analog offset that might be present in the analog signal. The analog offset settings can be independently adjusted for the colors Green1, Green2, Red, and Blue
and are programmed through registers 0x60, 0x61, 0x63, and 0x64, respectively. The user would need to program register 0x62 appropriately to enable the analog offset correction. The lower eight bits (bit[7-0]) determines the absolute value of the analog offset to be corrected and bit[8] determines the sign of the correction. When bit[8] is "1", the sign of the correction is negative and vice versa. The analog value of the correction relative to the analog gain stage can be determined from the following formula: Analog offset (bit[8] = 0) = bit[7-0] x 2mV Analog offset (bit[8] = 1) = - (bit[7-0] x 2mV)
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1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Column and Row Mirror Image
By setting bit 14 of Reg0x20, the readout order of the columns will be reversed, as shown in Figure 11.
Figure 11: Readout of Six Columns in Normal and Column Mirror Output Mode
LINE_VALID Normal readout DOUT9-DOUT0 Reverse readout DOUT9-DOUT0 Col5 (9:0) Col4 (9:0) Col3 (9:0) Col2 (9:0) Col1 (9:0) Col0 (9:0) Col0 (9:0) Col1 (9:0) Col2 (9:0) Col3 (9:0) Col4 (9:0) Col5 (9:0)
By setting bits 15 of Reg0x20 the readout order of the rows will be reversed, as shown in Figure 12.
Figure 12: Readout of Six Rows in Normal and Row Mirror Output Mode
FRAME_VALID Normal readout DOUT9-DOUT0 Reverse readout DOUT9-DOUT0 Row6 (9:0) Row5 (9:0) Row4 (9:0) Row3 (9:0) Row2 (9:0) Row1 (9:0) Row0 (9:0) Row1 (9:0) Row2 (9:0) Row3 (9:0) Row4 (9:0) Row5 (9:0)
By setting bits 15 and 7 of Reg0x20 the readout order of the rows will be reversed and maintain color order as shown in the figure below.
Figure 13: Readout of Six Rows in Normal and Row Mirror Output Mode with Color Order Maintained
FRAME_VALID Normal readout DOUT9-DOUT0 Reverse readout DOUT9-DOUT0 Row6 (9:0) Row5 (9:0) Row4 (9:0) Row3 (9:0) Row2 (9:0) Row1 (9:0) Row0 (9:0) Row1 (9:0) Row2 (9:0) Row3 (9:0) Row4 (9:0) Row5 (9:0)
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1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Column and Row Skip
By setting bit 3 of Reg0x20, only half of the columns set will be read out. An example is shown in Figure 14. Only columns with bit 1 equal to "0" will be read out (xxxxxxx0x). The row skip works in the same way and will only read out rows with bit 1 equal to "0." Row skip mode is enabled by setting bit 4 of Reg0x20. For both row and column skips, the number of rows or columns read out will be half of what is set in Reg0x03 or Reg0x04, respectively.
Figure 14: Readout of Eight Pixels in Normal and Column Skip Output Mode
LINE_VALID Normal readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) R2 (9:0) G3 (9:0) R3 (9:0)
LINE_VALID Column skip readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G2 (9:0) R2 (9:0)
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1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Black Level Calibration
The MT9M001 has automatic black level calibration on-chip which can be overridden by the user, as described below and shown in Figure 15. The automatic black level calibration measures the average value of 256 pixels from two dark rows of the chip for each of the four colors. The pixels are averaged as if they were light-sensitive and passed through the appropriate color gain. This average is then digitally filtered over many frames. For each color, the new filtered average is compared to a minimum acceptable level (to screen for too low a black level) and a maximum acceptable level. If the average is lower than the minimum acceptable level, the offset correction voltage for that color is increased by one offset LSB (offset LSBs do not match ADC LSBs; yypically, one offset LSB is approximately 2mV). If it is above the maximum level, the level is decreased by 1 LSB (2mV). The upper threshold is automatically adjusted upwards whenever an upward shift in the black level from below the minimum results in a new black level above the maximum. This prevents black level oscillation from below the minimum to above the maximum. The lower threshold is increased with the maximum gain setting (out of all four colors), according to the formula described under Reg0x5F. This prevents clipping of the black level. Whenever the gain or any of the readout timing registers is changed (shutter width, vertical blanking, number of rows or columns, or the shutter delay) or if the black level recalculation bit, reset bit or restart bit is set, the running digitally filtered average is reset to the first average of the dark pixels. The digital filtering over many frames is then restarted. Whenever the gain or the readout timing registers are changed, the upper threshold is restored to its default value. After changes to the sensor configuration, large shifts in the black level calibration can result. To quickly adapt to this shift, a rapid sweep of the black level during the dark-row readout is performed on the first frame after certain changes to the sensor registers. Any changes to the registers listed above will cause this recalculation. The data from this sweep allows the sensor to choose an accurate new starting point for the running average. This procedure can be disabled as described under Reg0x5F.
Figure 15: Black Level Calibration Flow Chart
Gain Selection (color-wise)
Pixel Output (signal minus reset)
X
+
10-bit ADC
ADC Data (9:0)
Offset Correction Voltage (color-wise)
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1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 7:
REGISTER
Black Level Registers
BIT DESCRIPTION
Reg0x5F This register controls the operation of the black level calibration thresholds. 15 No gain dependence. 1 = Thres_lo is set by the programmed value of bits 5-0, Thres_hi is reset to the programmed value (bits 14-8) after every black level average restart. 0 = Thres_lo and Thres_hi are set automatically as described below. 14-8 Thres_hi--maximum allowed black level in ADC LSBs (default = Thres_lo + 5). Black level maximum is set to this value when bit 7 = 1, black level maximum is reset to this value after every black level average restart if bit 15 = 1 and bit 7 = 0. 7 1 = override automatic Thres_hi and Thres_lo adjust (Thres_hi always = bits 14-8, Thres_lo always = bits 5-0). 0 = automatic Thres_hi and Thres_lo adjustment. 5-0 Thres_lo--Lower threshold for black level in ADC LSBs. Under default automatic operation (bit 7 = 0, bit 15 = 0), Thres_lo = RegGainmax/4 x (RegGainmax, bit 6 +1) x (RegGainmax, bit 7 +1), where RegGainmax is the maximum of the four independent gain register settings. Whenever a jump in the calibration causes the black level data to change from below Thres_lo to above Thres_hi, Thres_hi is adjusted according to the following: If new black level < 64: Thres_hi = Thres_lo + 2 + (2 x Delta), where Delta = new black level Thres_lo If new black level > 63 and < 119: Thres_hi = new black level + 4 If new black level > 119: Thres_hi = 123 After any recalculation of the black level and average restart, Thres_hi is reset to either Thres_lo + 5 (automatic, default mode), Thres_hi (bit 7 = 1). Reg0x62, bit 11 will override this. Reg0x62 This register is used to control the automatic black level calibration circuitry. 15 1 = do not perform the rapid black level sweep on new gain settings. 0 = normal operation. 14 Reserved--default is 0; do not change. 13 12 11 10-3 2-1 Reserved--default is 0; do not change. 1 = start a new running digitally filtered average for the black level (this is internally reset to "0" immediately), and do a rapid sweep to find the new starting point. 1 = do not reset the upper threshold after a black level recalculation sweep. 0 = reset the upper threshold after a black level recalculation sweep (default). Reserved--default is 1; do not change. Force/disable black level calibration. 00 = apply black level calibration during ADC operation only (default). 10 = apply black level calibration continuously. X1 = disable black level correction (Offset Correction Voltage = Skew Voltage = 0.0V). (In this case, no black level correction is possible). Manual override of black level correction. 1 = override automatic black level correction with programmed values. 0 = normal operation (default).
0
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Table 7:
REGISTER Reg0x60, Reg0x61, Reg0x63, Reg0x64
Black Level Registers (continued)
BIT DESCRIPTION These registers contain the 9-bit signed black level calibration values for the four colors in the Bayer pattern. In normal operation, these values are calculated at the beginning of each frame. However, if Reg0x62, bit 0 is set to "1," these registers can be written to, overriding the automatic black level calculation. This feature can be used in conjunction with readout of the black rows (Reg0x20, bit 11) if the user would like to use an external black level calibration circuit. The offset correction voltage is generated according to the following formula: Offset Correction Voltage = (9-bit signed calibration value, -256 to 255) * (2mV * Enable bit) 2's complement, if bit 8 = 1, Offset = bits [0-7] - 256 ADC input voltage = Pixel Output Voltage x Analog Gain - Offset Correction Voltage
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1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Still Image Capture with External Synchronization
In continuous mode video image capture, the TRIGGER signal should be held LOW or "0." To capture a still image, the sensor must first be put into snapshot mode by programming a "1" in register 0x1E, bit 8. In snapshot mode, the sensor waits for a TRIGGER signal (FRAME_VALID, LINE_VALID signals are LOW, pixel clock signal continues). When the TRIGGER signal is received (active HIGH), one frame is read out (a TRIGGER signal can also be achieved by programming a restart--for example, program a "1" to bit 0 of Reg0x0B). The reset, readout timing for that frame will be the same as for a continuous frame with similar register settings; the only difference is that only one frame is read out. General timing for the snapshot mode is shown in Figure 16.
Figure 16: General Timing for Snapshot Mode
TRIGGER Reset Row 1 Reset Row Reset Row x MAX strobe length (all rows integrating) STROBE MIN strobe length (1 row time) Readout
LINE_VALID Signal
By setting bit 9 and 10 of Reg0x20 the line valid signal can get three different output formats. The formats are shown when reading out four rows and two vertical
blanking rows (Figure 17). In the last format, the LINE_VALID signal is the XOR between the continuously LINE_VALID signal and the FRAME_VALID signal.
Figure 17: Different LINE_VALID Formats
Default FRAME_VALID LINE_VALID Continuously FRAME_VALID LINE_VALID XOR FRAME_VALID LINE_VALID
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Electrical Specifications Table 8:
SYMBOL VIH VIL IIN VOH VOL IOZ IPWRA IPWRD
DC Electrical Characteristics
DEFINITION Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Tri-state Output Leakage Current Analog Quiescent Supply Current Digital Quiescent Supply Current CONDITION MIN VPWR - 0.3 -0.3 -15 VPWR - 0.2 TYP 3.3 0.0 0.8 3.3 0.0 85 20 MAX VPWR + 0.3 0.8 15 UNITS NOTES V V A V V A mA mA
(VPWR = 3.3 0.3V; TA = 25C)
No Pull-up Resistor; VIN = VPWR or VGND
Default settings CLK_IN = 48 MHz; default setting, CLOAD = 10pF STDBY = VDD STDBY = VDD , CLK_IN = 0 MHz STDBY = VDD, CLK_IN = 48 MHz
50 16
0.2 15 110 24
IPWRA Standby IPWRD Standby IPWRD Standby ClkOn
Analog Standby Supply Current Digital Standby Supply Current Digital Standby Supply Current with Clock On
----
80 9 55
100 20 125
A A A
1 1
NOTE: 1. To place the chip in standby mode, first raise STANDBY to VDD, then wait two master clock cycles before turning off the master clock. Two master clock cycles are required to place the analog circuitry into standby, low-power mode.
Table 9:
SYMBOL FCLK_IN
t t t t t t t t t
AC Electrical Characteristics
DEFINITION Input Clock Frequency Clock Duty Cycle InputClock Rise Time Input Clock Fall Time CLK_IN to PIX_CLK propagation delay, LOWto-HIGH CLK_IN to PIX_CLK propagation delay, HIGHto-LOW CLK_IN to DOUT<9-0> propagation delay, LOW-to-HIGH CLK_IN to DOUT<9-0> propagation delay, HIGH-to-LOW Data Hold Time CLK_IN to FRAME_VALID and LINE_VALID propagation, LOW-to-HIGH CLK_IN to FRAME_VALID and LINE_VALID propagation, HIGH-to-LOW CLOAD = 10pF CLOAD = 10pF CLOAD = 10pF CLOAD = 10pF CONDITION MIN 1 45/55 TBD TBD -TYP 50/50 TBD TBD 11.5 11.5 13.5 13.5 13.1 CLOAD = 10pF TBD TBD -MAX 48 55/45 TBD UNITS MHz MIN/MAX ns ns ns ns ns ns ns ns ns ns
(VPWR = 3.3 0.3V; TA = 25C; CLK_IN at 48 MHz)
R F PLHP PHLP PHLD PHLD OH PLHF,L PHLF,L
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Propagation Delay for FRAME_VALID and LINE_VALID Signals
The LINE_VALID and FRAME_VALID signals change on the same falling master clock edge as the data output. The LINE_VALID goes HIGH on the same rising master clock edge as the output of the first valid pixel's data and returns LOW on the same master clock rising edge as the end of the output of the last valid pixel's data. As shown in the "Output Data Format" on page 4 and "Output Data Timing" on page 5, FRAME_VALID goes HIGH 242 pixel clocks prior to the time that the first LINE_VALID goes HIGH. It returns LOW at a time corresponding to (2 + Reg0x05-19 pixel clocks) after the last LINE_VALID goes LOW. Note that the data outputs change on the rising edge of the master clock.
Figure 18: Propagation Delays for FRAME_VALID and LINE_VALID Signals
tPLHFL tPHLFL
CLK_IN
CLK_IN
FRAME_VALID LINE_VALID tR
FRAME_VALID LINE_VALID tR
Figure 19: Propagation Delays for PIX_CLK and Data Out Signals
tR tF
CLK_IN
tPLHP tPLHP
PIX_CLK
tPLHD, tPLHD
tOH
DOUT (9:0)
DOUT (9:0)
DOUT (9:0)
DOUT (9:0)
DOUT (9:0)
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Two-Wire Serial Bus Timing
The two-wire serial bus operation requires certain minimum master clock cycles between transitions. These are specified in the following diagrams in master clock cycles.
Figure 22: Serial Host Interface Data Timing for Write
4 SCLK 4
Figure 20: Serial Host Interface Start Condition Timing
5 SCLK 4
SDATA
NOTE: SDATA is driven by an off-chip transmitter.
SDATA
Figure 21: Serial Host Interface Stop Condition Timing
5 SCLK 4
Figure 23: Serial Host Interface Data Timing for Read
5 SCLK
SDATA
SDATA
NOTE: All timing are in units of master clock cycle.
NOTE: SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip.
Figure 24: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
6 SCLK Sensor pulls down SDATA pin 3
SDATA
Figure 25: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
7 SCLK Sensor tri-states SDATA pin (turns off pull down) 6
SDATA
NOTE: After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a no acknowledge by leaving SDATA to float HIGH. On the following cycle, a start or stop bit may be used.
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1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Quantum Efficiency Figure 26: Quantum Efficiency - Color
Quantum Efficiency - Color
Blue 60 Green Red 50
Quantum Efficiency (%)
40
30
20
10
0 350
400
450
500
550
600
650
700
750
Wavelength (nm)
Figure 27: Quantum Efficiency - Monochrome
Quantum Efficiency - Monochrome
60 50 40 30 20 10 0 350
Quantum Efficiency (%)
450
550
Wavelength (nm)
650
750
850
950
1050
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1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Image Center Offset and Orientation Figure 28: Image Center Offset
7.75mm Pad 1
Pixel (0,0) Pixel (12, 20)
Pixel Array
0.015mm
Image Center
0.712mm 7.75mm Black and Boundary Pixels Die Center
Table 10: Optical Area Dimensions
OPTICAL AREA SXGA Chip Size, mm PIXEL Center of pixel (20, 12) Center of Pixel (1299, 1035) (including Seal Ring) X-DIMENSION 3,340.70m -3,315.2m 7.75mm Y-DIMENSION 3,372.45m -1,952.35m 7.75mm
NOTE: 1. X and Y coordinates referenced to center of die. 2. Die center = package center. 3. Image center offset from package center (x = 0.015mm, y = 0.712mm).
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Figure 29: Package Drawings
TOP VIEW BOTTOM VIEW SIDE VIEW
glass 1: 0.50 +/- 0.05 glass 2: 0.55 +/- 0.05
14.22 + 0.3/-0.15 SQ.
11.176 +/- 0.127 1.016 +/- 0.0762 1.52 +/- 0.254/-0.127
B I A
Pin No. 1 index
0.508 +/- -0.0762
H G
E
2.159 +/- 0.254
1
48 1
F D J C
48
1.016 +/- 0.178
Description A B C D E F G H I J Die thickness Glass thickness Base layer thickness Dam thickness Die attach bondline thickness Glass attach bondline thickness Sensor array to outer glass lid Sensor array to inner glass lid (air gap) Sensor array to seating plane Package total thickness
nominal 0.725 0.525 0.510 1.140 0.035 0.035 0.940 0.415 1.270 2.210
mm min 0.705 0.450 0.460 1.010 0.020 0.020 0.685 0.235 1.185 1.940
max 0.745 0.600 0.560 1.270 0.050 0.050 1.195 0.595 1.355 2.480
09005aef80a3e031 MT9M001_DS.fm - Rev. A 11/03 EN
28
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
PRELIMINARY
1/2-INCH 1.3 MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 30: Optical Orientation
Top of board
UP
Pixel Array
Pin 1
Bottom of board
Data Sheet Designation
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
09005aef80a3e031 MT9M001_DS.fm - Rev. A 11/03 EN Micron Technology, Inc., reserves the right to change products or specifications without notice.. (c)2003 Micron Technology, Inc
29

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